Quick Sizing & Sourcing Snapshot
- Manufacturer: GE (General Electric)
- Part Number: IS200BAPAH1A
- System Platform: Mark VI Speedtronic (Innovation Series)
- Hardware Type: Backplane Assembly (BAPA)
- Architectural Role: Acts as the passive motherboard in Mark VI cores (R1, S1, T1), distributing 28V DC power and routing VMEbus signals between processor and I/O cards.
- Key Specifications: 96-pin DIN 41612 Slots, 28V DC Input, Multilayer PCB, Conformal Coated (H1A).
System Architecture & Operational Principle
The is the passive backbone (BAPA) of a GE Mark VI turbine control cabinet, typically mounted vertically at the rear of the I/O Core (R1, S1, T1). It is not an active processor; it is the physical highway connecting the VME-based hardware.
It receives 28 V DC from the EPSM (Power Supply) via heavy-gauge wires landed on its input lugs or integrated terminal points. This power is then distributed across the P1/P2 (96-pin DIN 41612) connectors that populate the board—usually 10 to 12 slots wide.
- Slot 1/2 typically hosts the UCVE (Controller) or VCMI.
- Slots 3-9 host I/O and processing cards (DSPX, SIOB, TRLY, STCA).
The etched traces handle VMEbus arbitration, address decoding, and data transfer. In a TMR setup, three separate BAPA boards exist (one per core R, S, T), ensuring physical isolation; a short on the R-core backplane won’t drag down the S or T cores. This board operates at Level 2, providing the deterministic interconnect required for <20ms turbine protection voting.
Customer Value & Operational Benefits
Deterministic Signal Integrity
The etched trace geometry is calculated for VMEbus timing. Unlike point-to-point wiring where capacitance varies, the backplane ensures address strobes and data lines arrive with predictable skew. This is why a Mark VI executes a trip vote in <10ms without collision, directly impacting turbine safety availability.
Centralized Power Integrity
Uses solid copper planes to distribute +5V, +12V, -12V derived from the 28V input. This ensures the DSPX or UCVE sees a stiff 5V rail even when TRLY relays click shut (inrush). It reduces “Under Voltage” faults on the logic bus during transient loads.
Modular MTTR
Because I/O cards (SIOB, STCA) plug into this, you never touch field wires to swap a CPU. The field termination is on separate terminal boards (STCA, TBAI) cabled to the packs. This allows <5 minute processor swaps (cold) without disturbing 100+ field wires, slashing outage time.
Field Engineer’s Notes (From the Trenches)
The BAPA is the spinal cord. If you have intermittent “VME Bus Error” or “Processor Not Responding” that moves when you reseat cards, suspect the backplane pins before blaming a $5k CPU.
Focus on Slot 1 (Leftmost) and Slot 2 (Controller). These get the most insertion cycles. Use a jeweler’s loupe to check for splayed/twisted pins in the 96-pin DIN connectors. A pin 0.2mm out of alignment causes “half-seating”—power (Row B) works, data (Rows A/C) drops.
Clean the board annually with 90%+ Isopropyl Alcohol. In steam plants, mineral dust settles on bare fiberglass between connectors. Humidity spikes create surface leakage between the +5V plane and Ground, popping the 5V regulator on the EPSM.
CRITICAL: Never hot-swap the BAPA itself (obviously, it’s screwed down), but when inserting cards, ensure the ejector levers click squarely. A “cocked” card stresses the BAPA’s P1/P2 headers; over-torquing the faceplate screws can actually bow the backplane PCB, lifting pins in adjacent slots. Use a feeler gauge if you suspect bowing—a warped BAPA causes ghost interrupts that show up as “Random Processor Reboots” in the logs.
Real-World Applications
- Gas Turbine Control Core (<R1> Rack): Hosts the UCVE (Controller), DSPX (Processing), VVIB (Vibration), and SIOB (I/O). The BAPA ensures the 7FA gas turbine sequencing logic communicates deterministically between the voter and the I/O packs.
- Steam Turbine Trip Rack: Used in the <T> (Trip) core, hosting TRLY and TREG boards. The BAPA ensures the E-Stop command votes across the backplane to the TRLY outputs driving fuel trip solenoids with zero latency.
High-Frequency Troubleshooting FAQ
Q: My Mark VI rack loses communication with Slot 3 (SIOB) but Power LEDs are on. Is the BAPA bad?
A: Possibly, but check mechanical seating first. The 96-pin DIN needs force. If the ejector lever isn’t fully latched, Row B (Power) mates, but Rows A/C (Data) may misalign. Re-seat with firm, even pressure. If that fails, check Test Points on the BAPA for +5V at that slot’s area. No voltage = cracked trace on the backplane (rare, but vibration can fatigue FR4).
A: Only if the slot count and form factor match.
- BAPA = General I/O Core backplane.
- BPVC = Specific Controller backplane (often fewer slots, specific P2 wiring for UCVE).
- G1B is a revision (Artwork update).
Do not force a BPVC (Controller backplane) into an I/O core slot requirement; the P2 (I/O Bus) pinouts differ. For replacing a BAPA, stick to BAPA variants (H1A, G1B, GD) with the same slot count.
Q: The 28V DC is landed, but the UCVE in Slot 2 won’t boot (No “OK” LED).
A: Check Power Plane Continuity at the BAPA. Use a DMM on the P1 connector pins (Back of board, or via extender card). Pin 1/32 (+5V), Pin 6/63 (+12V). If 28V is in but +5V is 0V at the slot, the polyfuse/PTC on the BAPA for the +5V plane may have tripped from a prior short. Let it cool/reset, or inspect for a blown trace near the power input lugs.
Please note: The listed price is not the actual final price. It is for reference only and is subject to appropriate negotiation based on current market conditions, quantity, and availability.
