Quick Sizing & Sourcing Snapshot
- Manufacturer: GE (General Electric)
- Part Number: IS200EMIOH1A
- System Platform: EX2100 / EX2100e Excitation Control (Mark VI/VIe)
- Hardware Type: Exciter Main I/O Board (EMIO)
- Architectural Role: Acts as the central FPGA-driven signal aggregator in the control rack, managing I/O from terminal boards (ECTB, EACF, EXTB, EPCT) and routing gate pulses to the ESEL board.
- Key Specifications: Double-Height VME (Single Slot), FPGA Processing, 5V DC Backplane Power, 2 Front LEDs (Power/Status).
System Architecture & Operational Principle
The IS200EMIOH1A is an active, intelligent I/O processing board mounted in the EX2100 Control Rack, typically residing in the M1, M2, or C controller slots on the EBKP backplane.
Unlike passive terminal boards, the EMIO is the “brain” of the I/O layer:
- Signal Aggregation (Input): Via the P2 backplane connector, it collects data from four key terminal boards:
- ECTB (IS200ECTBG1A): Contact inputs (52G, 86G) and Trip Relay controls.
- EACF (IS200EACFGxB): Scaled AC feedback (Gen Volts/Current).
- EXTB (IS200EXTBG1A): De-excitation controls and field breakers.
- EPCT (IS200EPCTG1A): High-speed Power CTs and analog inputs.
- FPGA Processing: An onboard FPGA (Field Programmable Gate Array) processes these signals in real-time, validating contact states, scaling analog readings, and executing deterministic logic (e.g., checking interlocks).
- Control Execution (Output):
- Gate Pulses: Receives firing commands from the DSPX (via backplane) and forwards logic-level gate pulses to the ESEL (Exciter Selector) board. ESEL then distributes these to the EGPA/EHPAG1D amplifiers in the power cabinet.
- Relay Driving: Directly controls the 53A Field Flashing relays (via EXTB) and Pilot Trip relays on the ECTB.
- De-excitation: Initiates the sequence to trigger the EDEX (Crowbar) board via EXTB to discharge the rotor field safely during a trip.
The “H1A” suffix denotes specific trace routing optimizations and component grades for signal integrity in the EX2100 architecture.
Core Technical Specifications
- Form Factor: Double-Height, Single-Slot VME (Eurocard: ~9.25″ x 6.5″)
- Power Input: 5 V DC (Primary Logic, from EBKP Backplane P1)
- Processing: Onboard FPGA (Manages I/O logic, no separate CPU)
- Managed Terminal Boards: ECTB, EACF, EXTB, EPCT
- Downstream Links: ESEL (Gate Pulses), EXTB (De-excitation), ECTB (Relay Drivers)
- Front Panel LEDs:
- PWR (Green): 5V Logic Power Present.
- STATUS (Green/Activity): FPGA Initialized & Running (Often labeled IMOK).
- Connectors: P1 (Backplane Power/Comms), P2 (I/O Signal Bus to EBKP)
- Configuration: No Jumpers or DIP Switches (Configured via ToolboxST/Software).
- Isolation: Channel-to-Channel (Via Terminal Boards), Optical (To Power Stage)
- Environmental: 0°C to +65°C (Operational), Conformal Coated
Customer Value & Operational Benefits
Centralized I/O Logic (Reduced Complexity)
The EMIO consolidates the management of Contacts (ECTB), AC Signals (EACF), Power CTs (EPCT), and De-excitation (EXTB) into one VME slot. This eliminates the “spaghetti wiring” of discrete modules, reducing control rack slot usage by ~60% and cutting wiring errors by 40% during retrofits.
Deterministic Excitation Control
The onboard FPGA processes I/O with microsecond-level response. When the DSPX calculates a firing angle correction, the EMIO forwards the gate pulse to ESEL within <50 µs. This precision keeps generator terminal voltage stable within ±0.5% during load swings (e.g., 100MW step changes), preventing VAR hunting.
Seamless Redundancy Support
In TMR setups (M1/M2/C), this board is replicated. If the M1 EMIO fails, M2 takes over seamlessly. Its FPGA logic ensures that De-excitation commands (Crowbar) are executed reliably even during controller switchovers, protecting the rotor windings from overvoltage damage.
