Quick Sizing & Sourcing Snapshot
- Manufacturer: GE (General Electric)
- Part Number: IS200ICBDH1ABB (Base: IS200ICBDH1A)
- System Platform: Mark VI / Mark VIe (Innovation Series)
- Hardware Type: Innovation Control Board (ICBD – Main Processor)
- Architectural Role: Acts as the primary processing engine in Mark VI Innovation cores, executing turbine control logic (Speedtronic), PID loops, and managing I/O communication via the VME backplane.
- Key Specifications: 32-bit RISC CPU (200MHz), 8MB Flash (vs 4MB on H1A), 2MB FRAM, Dual Ethernet Front Panel.
System Architecture & Operational Principle
The is the “Brain” of the Mark VI Innovation Series control core, sitting at Purdue Level 2 (Control). Physically, it occupies a dedicated slot (usually Slot 1 or 2) in a VME-based control rack (I/O Core or Controller Core), interfacing with the VME P1/P2 Backplane.
Upstream, it talks to the HMI/Network via Dual Front-Panel Ethernet ports (IONet/UDH) and receives commands from the operator or higher-level DCS. Downstream, it communicates with I/O packs (PDIO, TCAT, STTC) and terminal boards (EACF, ECTB) via the VME bus and dedicated ribbon/fiber links.
The “Innovation” aspect is key: unlike the older fixed-function boards (like the UCVE), the ICBD is software-configurable. The onboard FPGA and 32-bit RISC CPU run the Speedtronic algorithms (Fuel Stroke, Acceleration, Temperature Control). It utilizes FRAM (Ferroelectric RAM) to store runtime variables (e.g., integrator states, sequence steps) without needing a battery. The “H1ABB” suffix indicates an extended memory variant (typically 8MB Flash vs the H1A’s 4MB) and component grading for high-reliability turbine applications.
Core Technical Specifications
- Processor: 32-bit RISC @ 200 MHz (Integrated FPU)
- Memory (Volatile): 2 MB SRAM (Runtime/Stack)
- Memory (Non-Volatile): 8 MB Flash (Firmware/Config), 2 MB FRAM (Retentive Variables)
- Backplane I/F: VME 96-pin (P1 Primary, P2 I/O Expansion)
- Front Ports: 2x RJ45 Ethernet (10/100M), 1x USB (Data Export), 1x RS-232 (Service)
- Logic Power: +5V DC (Sourced from Backplane/Power Supply)
- Real-Time Clock: Supercapacitor Backed (7-day hold-up, no battery required)
- Indicators: RUN (Green – Logic Active), FLT (Red – Hardware/Self-Test), ACT (Comms)
- Form Factor: 6U VME (Double-Height, Single-Slot)
- Environmental: -30°C to +65°C (Operational), Conformal Coated
Customer Value & Operational Benefits
Battery-Less Reliability (FRAM)
The inclusion of 2MB FRAM is the standout upgrade on the “ABB” variant. Traditional Mark VI cores (UCVE) used battery-backed SRAM; if the battery died or was removed too long, you lost sequence states and tuning constants, forcing a re-download and extending outage times. The ICBD retains variables through power cycles without batteries. This eliminates “Config Loss” scrambles during maintenance and removes the “Yearly Battery Check” PM task from your calendar.
Scalability for Complex Cycles (8MB Flash)
The “ABB” (8MB Flash) vs “H1A” (4MB) matters for Combined Cycle Startup Sequences. If you’re running complex logic (Multi-Fuel switching, HRSG drain sequencing, Synchronization logic) in a single core, the extra memory prevents “Memory Full” errors during commissioning. You avoid splitting logic across multiple cores, keeping turbine control centralized and reducing inter-core latency.
Software-Defined I/O (Innovation Flex)
Unlike the rigid Mark V/VI architecture, this board supports I/O Reallocation. If a specific I/O pack fails, you can remap the logic to a spare pack via ToolboxST without rewiring the field cabinet. In a forced outage scenario, this cuts MTTR (Mean Time To Repair) by 60%, as you’re reconfiguring software instead of pulling new homeruns.
Real-World Applications
- 9FA Combined Cycle (Innovation Retrofit): Replacing a vintage UCVE (Mark VI) with an in the Gas Turbine core. The 8MB Flash handles the expanded “Premix/Diffusion” fuel staging logic and HRSG interface scripts that the old 4MB UCVE couldn’t fit, eliminating the need for a separate “Aux Core.”
- Aeroderivative LM6000 (Offshore): Using the ICBD’s FRAM to survive frequent “Dead Bus” auto-restarts. During grid disturbances, the turbine drops offline; the FRAM retains “Last Valid Flame” and “Sequence Step” states, allowing a black-start in <5 minutes without operator re-initialization of control constants.
High-Frequency Troubleshooting FAQ
Q: ToolboxST shows “ICBD Board Healthy” but “I/O Packs Not Communicating” on specific channels.
A: 90% chance the P2 Backplane Connector isn’t mated. The ICBD uses P1 (Top) for power/address and P2 (Bottom) for high-speed I/O data.
- Power Down the rack (LOTO).
- Loosen faceplate screws.
- Visually inspect P2 pins (bottom of board) for splayed/bent contacts (common if a previous tech forced it).
- Reseat: Push center of faceplate firmly until both ejector levers click/sit flush. Tighten screws evenly.
- Power up. If P2 was the issue, “IONet Active” LEDs on the I/O packs should turn Green.
A: Hardware-wise, Yes (Form-Fit-Function). The H1ABB is backward compatible.
Software-wise: You shouldopen ToolboxST -> I/O Config -> Detect Hardware. It will see the “ABB” has 8MB Flash vs 4MB.
- If your project uses <4MB, it will run fine without changes.
- If you plan to use the extra memory, you must recompile/download the project so the OS allocates the full 8MB. Skipping “Detect” locks you to the old H1A memory map.
Q: “FLT” LED is Red, but “RUN” is Green. What’s the internal fault?
A: Check Diagnostic Registers in ToolboxST (Hardware Diagnostics -> ICBD -> Status).
- FPGA Config Error: Usually a seating issue (see P2 note above) or a corrupted download. Try “Reset” via software. If persistent, re-download the application (
.appl). - FRAM/Flash Checksum: Rare, but indicates memory corruption. Usually requires a “Cold Restart” (Power Cycle) and fresh download.
- Watchdog Trip: The CPU stalled. Often caused by a VME Bus Conflict (another board in the rack hogging the bus). Check other boards’ “ACT” LEDs.
Please note: The listed price is not the actual final price. It is for reference only and is subject to appropriate negotiation based on current market conditions, quantity, and availability.
