Quick Sizing & Sourcing Snapshot
- Manufacturer: GE (General Electric)
- Part Number: IS200DSPXH1D
- System Platform: Mark VI / EX2100 Excitation Control
- Hardware Type: Digital Signal Processor (DSP) Control Board
- Architectural Role: Executes high-speed math (PID, FFT) and excitation logic in the VME controller rack, offloading the main CPU (VCMI/UCVE).
- Key Specifications: 60 MHz DSP + ASIC, 3U Single-Slot, +5V DC Backplane Power.
System Architecture & Operational Principle
The lives in the VME rack of a GE Mark VI or EX2100 system, typically in Slot 2 or 3 of the Controller Core (M1, M2, or C). It sits on the P1/P2 backplane, drawing +5V DC and talking to the main processor and I/O boards (ERIO, VVIB).
Upstream, it gets raw digitized data (gen voltage/current, speed pulses) via VMEbus. Downstream, it crunches the heavy math: FFT for vibration, PID for AVR (Auto Voltage Regulator), and gate firing calculations for thyristor bridges. The ASIC (App-Specific Integrated Circuit) handles deterministic tasks (pulse generation) so the 60 MHz DSP isn’t interrupted. In TMR (Triple Modular Redundant) setups, three of these run in parallel, voting on logic to mask single-point failures. It operates at Level 2 (Control), interfacing Level 1 (Field I/O) with Level 3 (HMI/Coordination).
Core Technical Specifications
- Processor: 60 MHz Digital Signal Processor (DSP)
- Coprocessor: Custom ASIC (Deterministic Control/Firing Logic)
- Memory: FLASH (Firmware), RAM (Runtime), NVRAM (Retentive Vars)
- Backplane Interface: 96-pin DIN 41612 (P1 Primary, P2 I/O Expansion)
- Front Ports: P5 (DSP Emulator/JTAG), P6 (Eng Monitor/RS-232)
- Logic Voltage: +5 V DC (Primary), +12/-12 V DC (Aux/Indicators)
- Power Draw: ~10-15W (Requires adjacent slot airflow)
- Indicators: STATUS (Green/Activity), FAULT (Red/Diag)
- Form Factor: 3U VME (Single-height, ~100mm x 160mm)
- Environmental: 0°C to +60°C (Operational)
- Isolation: 1500 Vrms (Logic to I/O boundaries)
Customer Value & Operational Benefits
Math Offloading & Deterministic Control
This board is the calculus co-processor for the turbine. By running FFT (Vibration) and Excitation PID locally, it stops the main VCMI/UCVE CPU from choking during transients (e.g., generator load rejection). This keeps loop scans sub-20ms, critical for AVR stability and avoiding VAR oscillation during grid events.
TMR System Integrity
In a Triple Modular Redundant config, this board is built for 2oo3 (Two-out-of-Three) Voting. If a cosmic ray flips a bit or a BGA solder joint cracks on the ‘M1’ unit, the ASIC logic ignores the faulty node. The unit stays online (degraded/Simplex), avoiding a $50k+/hour unplanned outage for a single component glitch.
Firing Precision (EX2100)
The ‘H1D’ revision’s ASIC is tuned for Thyristor Firing. Swapping an older ‘H1A/B’ for ‘H1D’ often fixes historical timing skew in bridge firing pulses, reducing thyristor stress and balancing commutating reactor currents in EX2100 exciters.
Field Engineer’s Notes (From the Trenches)
Never hot-swap this board. The 96-pin P1/P2 carries +5V at high current. Sliding this out live risks arc flash; sliding it in causes voltage sag on the backplane, resetting the neighbor (VCMI). LOTO the EPSM for that core.
Inspect the BGA (Ball Grid Array) under the main DSP if “FAULT” is solid but the board is cool. After 15+ years of thermal cycling, those solder balls crack. A thermal camera shows the chip staying cold while regs heat up—classic BGA fracture.
The ‘D’ revision implies tighter timing. If mixing ‘H1D’ with ‘H1A/B’ in a TMR triplet, watch Vote Timing Skew in ToolboxST. Propagation delays differ; “Architecture Mismatch” or vote margin alarms pop during “TMR Align.” Keep R, S, T revisions matched (all H1D) in production.
