NI PXIe-5172
NI PXIe-5172
NI PXIe-5172
NI PXIe-5172

NI PXIe-5433 785118-01 | 2-Channel 80 MHz 16-Bit AWG – Field Service Notes

  • Model: PXIe-5433
  • Alt. P/N: 785118-01 (2 CH, 512 MB); 785117-01 (1 CH, 512 MB)
  • Product Series: PXIe-54×3 Arbitrary Waveform Generator Family
  • Hardware Type: 16-Bit, 80 MHz, 800 MS/s PXI Express Dual-Channel Arbitrary Waveform Generator
  • Key Feature: Independent per-channel generation engines with -92 dBc SFDR and 435 fs integrated jitter—each channel has its own trigger, marker, and script configuration without shared execution resources.
  • Primary Field Use: Generating precise dual-channel arbitrary and standard waveforms for automated semiconductor validation, automotive ECU testing, and aerospace/defense systems requiring phase-coherent multi-channel stimulus.
Get a Quote
In Stock
Manufacturer:
Part number: NI PXIe-5433 785118-01
Our extensive catalogue, including : NI PXIe-5433 785118-01 , is available now for dispatch to the worldwide. Brand:

Description

Hard-Numbers: Technical Specifications

  • DAC Resolution: 16 bits
  • Analog Bandwidth: 80 MHz (-3 dB)
  • DAC Update Rate: 800 MS/s
  • Maximum Arbitrary Waveform Rate: 400 MS/s (digital filter enabled), 250 MS/s (digital filter disabled)
  • Standard Function Range: 0 µHz to 80 MHz
  • Onboard Memory: 512 MB (785118-01)
  • Channel Count: 2 independent generation engines (no shared execution resources)
  • Output Type: Referenced single-ended
  • Connector Type: SMA (2 channels)
  • Output Impedance: 50 Ω
  • Load Impedance: Compensated for user-specified impedances
  • Output Coupling: DC (ground referenced)
  • Amplitude Range: 0.00775 Vpk-pk to 12 Vpk-pk (50 Ω load); 0.0155 Vpk-pk to 24 Vpk-pk (open load)
  • Offset Range: ±50% of Amplitude Range (Vpk-pk)
  • DC Accuracy (within ±5°C of self-calibration): ±0.35% of Amplitude Range ± 0.35% of Offset Requested ± 500 µV
  • AC Amplitude Accuracy (within ±5°C of self-calibration): ±1.0% ± 1 mVpk-pk
  • Passband Flatness: ±0.4 dB (1-80 MHz, <2.75 Vpk-pk)
  • Rise Time: 4.5 ns (<2.75 Vpk-pk), 5.4 ns (>2.75 Vpk-pk)
  • Spurious-Free Dynamic Range (SFDR) : -92 dBc (typical)
  • Integrated System Jitter: 435 fs
  • Channel-to-Channel Skew: ±110 ps (<2.75 Vpk-pk), ±275 ps (>2.75 Vpk-pk)
  • Sample Clock Rate: 800 MHz
  • Timebase Accuracy: Initial calibrated accuracy 1.5 ppm (warranted), time drift 1 ppm/year (warranted)
  • Reference Clock: Internal PXIe_CLK100 (backplane), 100 MHz (<±25 ppm)
  • Digital Filter: On/Off (removes frequency images when enabled)
  • Minimum Sample Rate: 5.6 µS/s (digital filter enabled), 10 S/s (digital filter disabled)
  • Self-Calibration: ~2 minutes
  • Warm-Up Time: 15 minutes
  • Operating Temperature: 0°C to 55°C
  • Storage Temperature: -40°C to 71°C
  • Relative Humidity: 10% to 90% noncondensing (operating), 5% to 95% noncondensing (storage)
  • Power Consumption: +3.3 V @ 2.3 A, +12 V @ 1.8 A; total 29 W
  • Dimensions: 3U one-slot PXI Express module, 21.6 cm × 2.0 cm × 13.0 cm (8.5 in × 0.8 in × 5.1 in)
  • Weight: 376 g (13.3 oz, 2 CH)
  • Bus Interface: PXI Express Gen 1 x4
  • Slot Compatibility: PXI Express or hybrid
  • Calibration Interval: 2 years
  • Compliance: IEC 61010-1, EN 61326-1, FCC Part 15B Class A
NI PXIe-5172

NI PXIe-5172

The Real-World Problem It Solves

Dual-channel benchtop function generators waste rack space and lock both channels to shared trigger resources. The PXIe-5433 (785118-01) puts two independent 800 MS/s generation engines in a single PXI slot with independent triggers, markers, and scripts—each channel runs completely autonomously without the other channel dragging it down.
Where you’ll typically find it:
  • Semiconductor ATE systems stimulating DUTs with phase-coherent I/Q pairs or differential analog stimuli requiring precise timing between channels
  • Automotive ECU test stands generating synchronized sensor and communication signals for functional validation under fault conditions
  • Aerospace/defense radar simulators producing dual-channel IF/RF waveforms with sub-picosecond skew for coherence testing
Bottom line: This AWG replaces two benchtop instruments in one PXI slot while delivering true independent dual-channel operation—no shared trigger bottlenecks, no forced synchronization, just two engines running their own shows.

Hardware Architecture & Under-the-Hood Logic

The PXIe-5433 (785118-01) sits on the PXI Express Gen 1 x4 backplane, drawing 29 W through +3.3 V and +12 V rails. The critical difference from single-channel or shared-engine competitors: each channel has its own FPGA-driven generation engine. They share only the reference clock and the external PFI trigger input (PXI backplane triggers are independent per channel). A Xilinx Kintex-7 FPGA handles fractional resampling for each channel independently, up-sampling user waveforms to 800 MS/s DAC rate while maintaining -92 dBc SFDR. Digital filtering per channel removes frequency images when enabled—disable it for 4.5 ns rise times at the cost of spectral purity. The 512 MB onboard memory stores waveform sequences, or stream via PCIe x4 for continuous generation.
  1. Waveform upload: Host PC loads waveforms to 512 MB onboard memory via PCIe Gen 1 x4 interface (3.2 GB/s max)
  2. Fractional resampling per channel: Each channel’s FPGA engine up-samples user waveforms to 800 MS/s DAC rate independently
  3. Digital filter stage (per channel, selectable): Removes frequency images when enabled for spectral purity; disable for fast rise times
  4. 16-bit DAC conversion per channel: Two independent DACs update at 800 MS/s, driven by separate generation engines
  5. Analog output stage per channel: Programmable gain and offset per channel; output impedance 50 Ω, DC-coupled, SMA connectors
  6. Clock distribution: Internal TCXO (1.5 ppm initial, 1 ppm/year drift) or PXIe_CLK100 backplane reference (±25 ppm) distributes 800 MHz sample clock to both DACs with 435 fs integrated jitter
  7. Synchronization: NI-TClk API aligns sample clocks using shared reference clock; channels auto-synchronize when in same NI-FGEN session with identical parameters
  8. Trigger system per channel: Rising edge triggers only; sources include PXI_Trig backplane (independent per channel), PFI lines (shared external input), software triggers
NI PXIe-5172

NI PXIe-5172

Field Service Pitfalls: What Rookies Get Wrong

Cross-Connecting Dual Outputs for Signal Summation
Technicians assume connecting Channel 0 and Channel 1 SMA outputs together will safely sum signals. The 50 Ω outputs are designed to drive loads, not other 50 Ω sources. While shorting to ground is safe per NI specs, cross-connecting outputs causes unpredictable signal levels and can stress output stages if one channel is high and the other low.
  • Field Rule: Never directly connect AWG outputs together. Use external resistive combiners with appropriate isolation for signal addition. Verify each channel drives its own 50 Ω termination or high-impedance load. If you need differential output, configure the channels as a differential pair—each channel drives its own side of the load, not each other.
Ignoring Independent Channel Engine Configuration
Engineers create a multi-channel session assuming both channels share trigger and marker settings. The PXIe-5433 has independent generation engines—channels do NOT automatically inherit each other’s configuration unless explicitly set in a single NI-FGEN session.
  • Field Rule: Decide upfront: independent sessions (each channel its own session) for completely autonomous operation, or single multi-channel session for synchronized operation. In multi-channel mode, explicitly configure triggers and markers for both channels—they don’t share by default. Remember: independent engines mean independent configuration.
Forgetting Passband Flatness Degradation at High Ambient
Rookies assume ±0.4 dB passband flatness applies across 0-55°C. Above 45°C ambient with sine frequencies ≥40 MHz, add ±0.015 dB/°C to the spec. At 55°C running 80 MHz sine, you’re looking at ±0.55 dB flatness—kills calibration accuracy in high-frequency applications.
  • Field Rule: Monitor chassis inlet temperature. If ambient exceeds 45°C, account for ±0.015 dB/°C additional flatness degradation for signals ≥40 MHz. For critical calibration work, keep ambient below 45°C with external cooling or relocate the rack. Passband flatness is warranted at 0-55°C, but the temperature coefficient kicks in above 45°C for high-frequency signals.
Enabling Flatness Correction with Dynamic Digital Gain Changes
Users enable flatness correction then try to change digital gain on-the-fly. Flatness correction requires pre-computed digital correction coefficients—you cannot change gain without recomputing or disabling correction.
  • Field Rule: Disable flatness correction before changing digital gain, or pre-compute gain-adjusted waveforms before upload. For applications requiring on-the-fly gain adjustment, accept reduced passband flatness. Flatness correction locks gain settings; dynamic gain needs correction disabled.
Disabling Digital Filter for Fast Edges Without Accounting for Aliasing
Field engineers disable the digital filter to get 4.5 ns rise times on square waves but don’t realize frequency images corrupt downstream measurements. The filter removes aliasing; disabling it includes high-frequency junk that shows up as spurs in spectral analysis.
  • Quick Fix: Disable filter only for time-domain applications where rise time matters (pulse generation, digital stimulus). Enable filter for frequency-domain work (sine waves, modulated signals) where spectral purity matters. Remember: 4.5 ns rise time = spectral trash in frequency domain. Pick your poison—fast edges or clean spectrum.

Commercial Availability & Pricing Note

Please note: The listed price is for reference only and is not binding. Final pricing and terms are subject to negotiation based on current market conditions and availability.

Related products