Description
Key Technical Specifications
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Model Number: DS200SDCCG1AFD
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Manufacturer: General Electric
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Processors: Three 16-bit TMS320C25 DSPs (master, comms, I/O)
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Memory: 128 kB dual-ported RAM (DPR) per CPU, 256 kB EPROM firmware
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Power Demand: +5 V @ 6 A, ±15 V @ 0.5 A, +24 V @ 0.2 A via 2PL back-plane
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I/O Buses: 40-pin DPR link to SDCI, 34-pin analog, 40-pin LAN to SLCC
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Isolation: 1500 Vdc port-to-port, 500 Vdc channel-to-ground
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Data Rate: 10 MHz DPR hand-off, 1 Mbps LAN token ring
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Watchdog: 50 ms tick; fault trips stack within 100 ms
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Reset: Push-button on faceplate; also software initiated
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Temperature: –20 °C to +70 °C operating
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Board Size: 203 × 178 × 25 mm, 0.9 kg; conformal-coated “normal” grade
DS200SDCCG1AFD
Field Application & Problem Solved
In a paper-mill DC sectional drive the line keeps sagging and the old analog regulator cards drift with temperature. You retrofit the machine with a DC2000 stack and drop a DS200SDCCG1AFD in slot 2. This card becomes the brain: it reads tacho volts, armature current, dancer position, and executes the speed loop every 2 ms. Because the three CPUs split the job—one handles field-bus, one crunches the PID, one manages gate firing—you don’t get scan-time overruns when the operator slams in a 30 % speed reference. The dual-port RAM means the comms CPU can shove a new speed set-point while the I/O CPU is still firing SCRs; no wait states, no missed pulses. End result: the paper machine stays in registration, you scrap less sheet, and you finally get rid of those temperamental analog cards that used to drift 2 % every shift.
In a paper-mill DC sectional drive the line keeps sagging and the old analog regulator cards drift with temperature. You retrofit the machine with a DC2000 stack and drop a DS200SDCCG1AFD in slot 2. This card becomes the brain: it reads tacho volts, armature current, dancer position, and executes the speed loop every 2 ms. Because the three CPUs split the job—one handles field-bus, one crunches the PID, one manages gate firing—you don’t get scan-time overruns when the operator slams in a 30 % speed reference. The dual-port RAM means the comms CPU can shove a new speed set-point while the I/O CPU is still firing SCRs; no wait states, no missed pulses. End result: the paper machine stays in registration, you scrap less sheet, and you finally get rid of those temperamental analog cards that used to drift 2 % every shift.
Installation & Maintenance Pitfalls (Expert Tips)
Flash the right firmware revision
AFD ships blank EPROM. If you drop in a board with old rev B firmware on a rev D drive, the gate firing table is wrong and you’ll blow 1200 A semis on the first start. Always burn the latest .BIN file from the toolbox before you leave the shop.
Flash the right firmware revision
AFD ships blank EPROM. If you drop in a board with old rev B firmware on a rev D drive, the gate firing table is wrong and you’ll blow 1200 A semis on the first start. Always burn the latest .BIN file from the toolbox before you leave the shop.
Latch the DPR connector first
The 40-pin DPR header is keyed, but the shroud is soft plastic. Half-latch it, power up, and you get random bit flips that look like a bad tach. Push until you hear the second click, then tug-test.
The 40-pin DPR header is keyed, but the shroud is soft plastic. Half-latch it, power up, and you get random bit flips that look like a bad tach. Push until you hear the second click, then tug-test.
Watchdog LED is not a power LED
New guys see the green LED and assume the card is healthy. That LED only means the 5 V rail is up; the watchdog flashes once per 50 ms tick. No flash = CPU hung, swap the board.
New guys see the green LED and assume the card is healthy. That LED only means the 5 V rail is up; the watchdog flashes once per 50 ms tick. No flash = CPU hung, swap the board.
DS200SDCCG1AFD
Capacitor kit every 12 years
The 22 µF, 35 V tantalums on the 5 V rail dry out. ESR climbs, ripple doubles, and you start getting “SDCI LINK FLT” at 40 °C. Replace all six during the outage; five minutes of SMD work beats a forced outage when the board crashes at full load.
The 22 µF, 35 V tantalums on the 5 V rail dry out. ESR climbs, ripple doubles, and you start getting “SDCI LINK FLT” at 40 °C. Replace all six during the outage; five minutes of SMD work beats a forced outage when the board crashes at full load.
Technical Deep Dive & Overview
The SDCC is a triple-DSP architecture riding on the Mark V back-plane. CPU-A (master) owns the speed loop, field weakening, and protection; CPU-B (LAN) handles Genius, Modbus, and SLCC token-pass; CPU-C (I/O) services A/D, gate pulses, and contactor drivers. Dual-port RAM eliminates bus arbitration delays—each CPU sees the same data array without hand-shake overhead. Firmware is stored in soldered EPROM; a serial boot-loader on CPU-A lets you field-flash through the 9-pin diagnostic port. No on-board power devices—just 5 V logic—so the card runs cool and can be swapped live: pull the old one, slam in the new, hit reset, and the drive re-syncs in under five seconds.
The SDCC is a triple-DSP architecture riding on the Mark V back-plane. CPU-A (master) owns the speed loop, field weakening, and protection; CPU-B (LAN) handles Genius, Modbus, and SLCC token-pass; CPU-C (I/O) services A/D, gate pulses, and contactor drivers. Dual-port RAM eliminates bus arbitration delays—each CPU sees the same data array without hand-shake overhead. Firmware is stored in soldered EPROM; a serial boot-loader on CPU-A lets you field-flash through the 9-pin diagnostic port. No on-board power devices—just 5 V logic—so the card runs cool and can be swapped live: pull the old one, slam in the new, hit reset, and the drive re-syncs in under five seconds.
